1. Field of the Invention
The present invention relates to the field of digital electronic systems. More particularly, the present invention relates to the field of interface circuits used for the communication of information between two or more electronic domains or subsystems wherein one or more circuit portions functions as a slave interface.
2. Related Art
Designs of computer systems and computer system architectures today can include the combination of one or more different subsystems with each subsystem having a different bus architecture or protocol. Subsystems are combined to facilitate the implementation of larger systems and typically known and standard subsystems are the ones selected for combining. By using known and standard subsystems, design time, manufacturing costs, design complexity, system maintenance and trouble shooting can all be reduced advantageously.
One standard bus architecture is the Peripheral Component Interconnect (PCI) bus standard. Computer systems can communicate with coupled peripherals using different bus standards including the PCI bus standard, or alternatively, using the Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) bus standards. Recently, the IEEE 1394 serial communication standard has become a popular bus standard adopted by manufacturers of computer systems and peripheral components for its high speed and interconnection flexibility. Another interface bus (developed for the ARM processor) is the Advanced Microcontroller Bus Architecture (AMBA) which defines the Advanced System Bus (ASB). The Advanced RISC Machine (ARM) processor is a special purpose, user-customizable RISC processor. Each of the above communication standards communicates information (e.g., in data packets) using different bus protocols particular to the bus architecture.
Interconnected subsystems of an integrated circuit design do not necessarily communicate or operate using the same bus protocols. Due to the many bus architecture standards available within computer systems and communication systems, it is often the case that one computer (or device) of one bus standard or xe2x80x9cbus protocol domainxe2x80x9d is coupled to and communicates with another computer (or device) of another bus standard having another different bus protocol. Since the bus standards are not necessarily compatible, bridge circuits or xe2x80x9cinterface circuitsxe2x80x9d have been used in the prior art to generate special handshaking signals, or otherwise function, to allow communication from one bus domain to another. The interface circuit is physically coupled between the two bus domains and is thereby made available to receive and send data or control information between the bus domains.
The prior art configuration 5 of FIG. 1 shows a host computer""s general Central Processing Unit (CPU) 10 interfaced to a Peripheral Component Interconnect (PCI) bus (or device) 14 via a Northbridge integrated circuit device 12. The Northbridge device 12 is commercially available for that use. Similarly, the Southbridge device 16 is also readily available for purposes of interfacing a general purpose CPU 10 to an ISA device 18.
Unlike commercially available CPUs, the Advanced RISC Machine (ARM) processor is a special purpose, user-customizable RISC processor which is very well suited to processor-intensive functions, such as handwriting recognition and other real-time digital signal processing applications for data and voice communications. With ARM""s small 32 bit RISC CPUs, integrated, high performance designs can be custom developed for relatively very fast time-to-market and low product development costs.
PCI-based computer peripheral devices are used extensively in host computer systems and are readily available commercially. One reason why the ARM processor has not been combined with a PCI device is due to the fact that host computers use general purpose CPUs, which can be interfaced to PCI devices using the Northbridge solution.
Embedding an ARM processor for a specialized subsystem function, such as within a network adapter interface card, can significantly improve the overall host system performance since it lessens the need to use the host CPU for the subsystem networking functions. So, to the extent that an embedded processor can perform the network subsystem processor functions, it frees up the host CPU for other higher priority processing tasks. However, use of an ARM processor embedded within the network adapter subsystem can only be advantageous if the ARM processor can be interfaced to communicate with a PCI-based host CPU and other PCI peripheral devices through the PCI bus.
One interface bus developed for the ARM processor is the Advanced Microcontroller Bus Architecture (AMBA) which defines the Advanced System Bus (ASB). However, the bus protocols are different between the PCI and ASB domains, for instance, the AMBA ASB bus and the PCI bus operate at different clock frequencies and have different signaling schemes for data communication. Unlike the Northbridge device which exists to interface between general purpose CPUs and the PCI bus, there are no known devices for bridging between the ARM processor and a PCI interface bus.
Accordingly, the present invention provides an interface circuit for providing communication between subsystem domains having different bus protocols within an electronic system. The present invention provides a pipelined interface circuit that provides the above communication without performance degradation by allowing each bus domain to operate at its optimum frequency and standard. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.
A slave interface circuit is described herein for providing communication between a PCI bus domain and an AMBA ASB bus domain. The novel circuit is an integrated interface for communicating using ASB protocol and translating ASB commands into PCI like commands. Embodiments include interfaces that are particularly suited for FPGA (field programmable gate array) and ASIC (application specific integrated circuit) implementations. A high-speed embodiment is also discussed offering prefetch functionality. The slave interface circuit of the present invention uses pipelined circuit stages to effectively manage the problem where the AMBA bus specifications require an ASB command to be issued on the falling edge of the ASB clock (B_CLK) and the associated data is to be provided on the following falling edge of the B_CLK. Generally, pipeline architecture of the slave interface circuit allows the bus protocols to operate at optimum speed and supports the natural flow of data between the AMBA ASB and PCI domains without the need for wait cycles. Pipelined ASB burst cycles are supported.
Input latches catch ASB commands on the falling edge of the ASB clock (B_CLK) and then circuits are used to reformat the data using size information (B_SIZE) and address bits (B_ADDR) from the ASB bus and swap bytes and generate the required byte enable (BEN) signals. The invention allows byte, halfword (2-byte) and fullword (4-byte) accesses. Byte readback data are provided on all four byte lanes and halfword readback data are provided on both halfword lanes. The reformatted data is latched into a set of request registers on the next rising edge of the ASB clock. A clock boundary crossing circuit can be used to handshake the data to a second independent clock domain. The ASB slave interface circuit runs on the ASB clock while the service agents may be running on a totally independent second clock.
During an ASB read request, the read data is latched on the rising edge of the ASB clock such that an ASB master agent can latch its requested data on the next falling edge of the ASB clock. The other handshake signals (B_WAIT, B_LAST and B_ERR) are latched on the falling edge of the ASB clock and the output enable is asserted during the low duration of the edge of the ASB clock. The ASB master agent can sense the handshake on the rising edge of the ASB clock.
Specifically, embodiments of the present invention include a pipelined interface circuit comprising: an input latch circuit for receiving and holding address and size signals from a first bus domain; a hold circuit for receiving and holding outputs from the input latch circuit and for receiving and holding data signals from the first bus domain wherein the data signals arrive one clock cycle behind the address and size signals; a first data translate and replicate circuit coupled to the hold circuit and for reformatting the data signals into first formatted data signals which are formatted for a second bus domain; and a request circuit for receiving outputs from the first data translate and replicate circuit and for receiving outputs from the hold circuit, the request circuit for generating a request to the second bus domain and for simultaneously providing the second bus domain with the address signals, the first reformatted data signals and byte enable signals and wherein the input latch circuit, the hold circuit and the request circuit are all clocked by a clock signal of the first bus domain. The above embodiment is particularly suited for FPGA applications. Embodiments include the above and wherein the first bus domain is compliant with the ASB bus standard and wherein the second bus domain is compliant with the PCI bus standard. Embodiments also include an implementation specific for ASIC designs and also a high performance implementation using prefetch circuitry.